JVC DT-V24G1 Manual De Instrucciones página 13

Computer signals (preset)
DVI-D (HDCP) terminals
Resolution
No. Signal name
Horizontal
1 VGA60 640
2 WVGA60 852
3 SVGA60 800
4 XGA60 1024
5 WXGA (1280) 1280
6 WXGA+60 1440
7 SXGA60 1280
8 WSXGA+60 1680
9 UXGA60* 5 1600
10 WUXGA60* 5 1920
11 720/60p 1280
12 1080/60p* 1920
5
13 720/50p 1280
14 1080/50p* 5 1920
* For DT-V20L3G: When No. 9, 10, 12 or 14 signals come in, thin lines will become obscured because their signal
5
resolution is higher than the screen resolution.
• Non-preset signals may not be displayed normally even if their frequency is within the acceptable range (☞
"Horizontal/vertical frequency (computer signal)" on page 26).
• When a preset signal comes in, the signal format is shown on the status display. For other signals, the
resolution is shown.
Frequency
Horizontal
Vertical Vertical (Hz)
(kHz)
480 31.5 59.9
480 31.5 59.9
600 37.9 60.3
768 48.4 60.0
768 47.8 60.0
900 55.9 60.0
1024 64.0 60.0
1050 65.2 60.0
1200 75.0 60.0
1200 74.0 60.0
720 45.0 60.0
1080 67.5 60.0
720 37.5 50.0
1080 56.25 50.0
Specification of the DVI-D (HDCP) terminal
Connect it to the DVI-D output terminal on a personal computer.
Pin
Scan system
No.
1 T.M.D.S Data 2–
Non-interlace
2 T.M.D.S Data 2+
Non-interlace
3 T.M.D.S Data 2 shield
Non-interlace
4 NC
Non-interlace
5 NC
Non-interlace
6 DDC Clock
Non-interlace
7 DDC Data
Non-interlace
8 NC
Non-interlace
Non-interlace
NOTE
Non-interlace
Non-interlace
Status indication of DUAL LINK/3G SDI signal information
Non-interlace
When DUAL LINK and 3G SDI signals come in, the status of DUAL LINK is displayed. When "SDI DUAL
Non-interlace
LINK" (☞ page 12) in MAIN MENU is set to "OFF" and a 3G SDI signal comes in, the 3G SDI signal
Non-interlace
information is displayed.
Status indication of DUAL LINK
When "SDI DUAL LINK" (☞ page 12) in MAIN MENU is set to "ON" and an SDI signal is selected, "DUAL
LINK" is displayed.
Status indication of 3G SDI signal information
Following signal information can be displayed when a 3G SDI signal comes in.
3G A-1: Level A mapping structure 1
3G A-2: Level A mapping structure 2
3G A-3: Level A mapping structure 3
3G A-4: Level A mapping structure 4
3G B-DS1: Level B data stream 1
3G B-DS2: Level B data stream 2
3G B-DUAL: Level B DUAL LINK
Pin
Input signal Input signal
No.
9 T.M.D.S Data 1–
10 T.M.D.S Data 1+
11 T.M.D.S Data 1 shield
12 NC
13 NC
14 +5 V Power
15 GND
16 Hot Plug Detect
Pin
Input signal
No.
17 T.M.D.S Data 0–
18 T.M.D.S Data 0+
19 T.M.D.S Data 0 shield
20 NC
21 NC
22 T.M.D.S Clock shield
23 T.M.D.S Clock+
24 T.M.D.S Clock–
11
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