Diagramas De Bloques I/O - LG DR385 Manual De Servicio

3. DIAGRAMAS DE BLOQUES I/O

E2P E2P
ROM RO
I2C_CLK
I2C_DATA
XRST_IO
AU AUDIO DIO
AD ADC
MM1763 MM1763
AIN_SCLK
AIN_MCLKOUT
AIN_FSYNC
AIN_DO
AUDIO AU DIO
DAC DAC
AOUT_FSYNC
AOUT_DO
AOUT_SCLK
AOUT_MCLK
DAC_CS
HOST_DATA_IN
HOST_CLK_IN
BCLKIN
PCKIN
LRCKIN
ADIN
SEN, SCK, SDATLSEN, LSCK, LSDATRSEN,
RSDAT,TGCHG,
WBLDIF,TKDRV,EQOUT[A:B], SE01,SE02,W
AN221 AN22116A 16A
BL,WTGE,SH[1:4 ],SH6,TC,CLUMPG E,ASEN
(RF (RF IC IC)
V,LPPS,OFTR,BDO.
LO LOADER ADER
CONNE NNECTOR CTOR
(F (FOR T TES EST)
Solamente para uso interno de LGE
TUNER TUNER
I2C_CLK
I2C_DATA
HOST_ENA_L
HOST_CLK_IN
HOST_DATA_IN
HOST_DATA_OUT
DRAM DRAM
DDR_DQS[ 0:1]
DDR_DM[0:1]
DDR_WE, DDR_CS
DDR_CAS, DDR_RAS
DDR_BA[0:1] XIRQ1/ PIO21
DDR_CKE SBT0/P I041
DDR_CLK, DDR_NCLK SBO0/P I042
DDRDQ0[1:15] ,DDR_A[ 0:12] SBIO/P IO40
LPCKIOOUT
ADOUT
BCKIOOUT
PCKIOOUT
XIRQ2/ PIO22
HOST_DATA_IN
HOST_CLK_IN
ATA1_DMARQ
ATA1_WR
ATA1_RD
ATA1_IORDY
ATA1_DMAACK
ATA1_INTRQ
/ATA1_CS0
/RST_ATA1
/ATA1_CS1
NDASP
NPDIAG
ATA1_ADD[ 0:2]
ATA1_D[ 0:15]
3-17
I/O I/O BOARD
10MHz 32.768MHz
I/ I/ O MICOM
HOST_RST_L
FLASH FLASH
XSCS0
XSRE
JTAG JTAG
XSWE0
SA[ 0:21]
DEBUG DE BUG
SD[0:15]
DRMON
SUPPORT
EXTRG
TMS
TDO,TDI
TCK
27MHz
SYSCLK, XSCS1,XSCS2
TXD[ BE
XSWE0,XSDK,XSRE
XIRQ4/ PIO24,SRXW
XTRST
MV3 MV3
XRST
CLK54OUT
CLK27OUT
DAFLG
SPDRV
DAOUT
STEP_A_DRV
EEPROM_CLK ADFLG, GCP
STEP_B_DRV
EEPROM_DIN SCL0/P I032
TRK_LOD_DRV
EEPROM_CS SDA0/ PI030
TITL_DRV
FOCUS_DRV
CIN[ 0:5]
FG
YIN[0:5]
EEPROM EEPROM
BD7956 BD7956
MOTO MO TOR R DRIVE
3-18
TIMER B TIM R BOARD OARD
RMC_IN
FLD_CLK FL FLD
FLD_ENA_L
DRIVER DR
FLD_DATA_OUT
KEY_RTN_[0:1]
ANALOG_XRST
MAIN BOARD MAIN BOARD
XRST_IO
XRST_IO
XTRST
TXD,RXD
4P 4P CN CNT
PPORT
XRST_IO
CARD CA RD
BE, ],RX D[ BE BE, ]
FE FE
XRST_IO
IC IC301 301
AN133 AN13351 51
(V. (V.DEC EC)
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