Publicidad
Idiomas disponibles
Idiomas disponibles
5
2
ET_MDC
2
ET_MDIO
D
2
ET_TXD0
2
ET_TXD1
2
ET_TX_EN
2
ET_TX_CLK
2
ET_COL
2
ET_RXD0
2
ET_RXD1
50MHz CLOCK OUT
Generate by IP101A
C
use 25M crystal
X2_OUTPUT
VDD33
R414
R414
100K
100K
B
C215
C215
0.1u
0.1u
R442
R442
VDD33
R168
R168
4.7K
4.7K
R154
R154
2
ETH-RST
A
5
4
ET_MDC
VDD33
ET_MDIO
R403
R403
5.1K
5.1K
ET_TXD0
ET_TXD1
ET_TX_EN
ET_MDC
25
ET_MDIO
26
ET_TX_CLK
ET_TXD0
6
ET_TXD1
5
ET_COL
4
3
ET_RXD0
ET_TX_EN
2
7
ET_RXD1
ET_TX_CLK
R406 0R
R406 0R
50MHz_CLKOUT
ET_COL
22
ET_RXD0
21
20
ET_RXD1
50MHz_CLKOUT
19
18
16
R401
R401
5.1K
5.1K
1
VDD33
23
R399
R399
5.1K
5.1K
ET_RX_ER
24
Set IP101A
X1_INPUT
46
X2_OUTPUT
47
to RMII Mode
VDD33
VDD33
14
R416 5.1K
R416 5.1K
ET_INT_LAN
48
*
LINK
9
DUPX
10
12
Y3
Y3
10ACT
NC/25MHz
NC/25MHz
100ACT
13
2
1
X1_INPUT
COL
15
R422
R422
11
47R
47R
C214
C214
C259
C259
17
33p
33p
33p
33p
45
CRYSTAL
Pin48 could be short VDD33 if
as close as to chip
interrupt funtion is not used.
33V_Normal
L48
L48
0R
0R
1,2,3,7
33V_Normal
+
+
VD6
VD6
CA131
CA131
NC/1N4148
NC/1N4148
47uF/25V
47uF/25V
RST_LAN
As close to IP101A
R404
R404
NC/0R
NC/0R
Pin14 as possible
NC/10K
NC/10K
ICC < 200mA
33V_Normal
NC/10k
NC/10k
1
V21
V21
NC/3904
NC/3904
L49
L49
FB220/300mA
FB220/300mA
+
+
CA133
CA133
47uF/25V
47uF/25V
As close to IP101A
Pin36 as possible
4
3
AVDD33
N23
N23
IP101ALFX
IP101ALFX
36
AVDD33
MDC
AVDD33
8
REGIN
MDIO
REGIN
32
REGOUT
TXD0
REGOUT
TXD1
29
TXD2
AGND
35
TXD3
AGND
BANDGAP
TX_EN
RESISTOR
REF_CLK
CRS_DV
28
R447
R447
IP101A
RXD0
ISET
6.19K/1%
6.19K/1%
RXD1
RXD2
34
RXD3
MDI_TP
C50M_O
33
COL
MDI_TN
CRS/LEDMOD
31
RX_ER
MDI_RP
X1
30
X2
MDI_RN
27
TEST_ON
DVDD33
37
INTR
AN_ENA
38
DPLX
39
PHYAD0/LED0
SPD
40
PHYAD1/LED1
RPTR
41
PHYAD2/LED2
APS
43
PHYAD3/LED3
ISOL
44
PHYAD4/LED4
MII/SNIB
42
RST_LAN
DGND
RESET_N
DGND
DGND
VDD33
REGOUT
R441
R441
0R
0R
+
+
C161
C161
C212
C212
CA132
CA132
0.1u
0.1u
0.1u
0.1u
47uF/25V
47uF/25V
As close to IP101A
Pin32 as possible
** Bead should be placed as close to IP101A
as possible and in the same side as IP101A.
* : Optional ,but recommended
AVDD33
C283
C283
0.1u
0.1u
3
2
PLACA MAIN 1815 VER.C
10ACT
C213
C213
VD15
VD15
BAT54C
BAT54C
0.1u
0.1u
100ACT
XP4
XP4
RJ45
RJ45
1
TX+
ACT_LED_C
4
TXOCT
ACT_LED_A
2
TX-
LNK_LED_C
3
RX+
LNK_LED_A
5
RXOCT
6
RX-
SHLD1
SHLD2
7
(NC)
15
REGOUT
8
GND
16
C171
C171
C177
C177
C217
C217
0.1u
0.1u
10n
10n
10n
10n
C218 1nF/2KV
C218 1nF/2KV
C246 1nF/2KV
C246 1nF/2KV
L47 FB220/300mA
L47 FB220/300mA
REGIN
**
LED and PHY address
C216
C216
C194
C194
0.1u
0.1u
10n
10n
Configuration
This schematic sets
As close to IP101A
PHY address to 00001b.
Pin8 as possible
PHYADDR0
LINK
PHYADDR1
DUPX
PHYADDR2
10ACT
PHYADDR3
100ACT
PHYADDR4
COL
LED0
LED1
LED2
Link
Dupx
10Act
Title
Title
Title
Size
Size
Size
Date:
Date:
Date:
2
1
ACT_LED
14
R421
R421
510R
510R
LINK
13
VDD33
12
ACTIVITY
R400 510R
R400 510R
11
ACT_LED
9
10
15
16
Nick.Liu modify 090325
VDD33
R444
R444
5.1K
5.1K
R445
R445
5.1K
5.1K
R439
R439
5.1K
5.1K
R423
R423
5.1K
5.1K
R458
R458
5.1K
5.1K
LED3
LED4
100Act
COL
MStar Semiconductor, Inc
MStar Semiconductor, Inc
MStar Semiconductor, Inc
4F-1, No. 26, Tai-Yuan St., ChuPei,
4F-1, No. 26, Tai-Yuan St., ChuPei,
4F-1, No. 26, Tai-Yuan St., ChuPei,
Hsinchu Hsien, Taiwan 302, R.O.C
Hsinchu Hsien, Taiwan 302, R.O.C
Hsinchu Hsien, Taiwan 302, R.O.C
VIF 256p demo Board
VIF 256p demo Board
VIF 256p demo Board
Document Number
Document Number
Document Number
A3
A3
A3
ETHERNET_PHY
ETHERNET_PHY
ETHERNET_PHY
Tuesday, July 07, 2009
Tuesday, July 07, 2009
Tuesday, July 07, 2009
Sheet
Sheet
Sheet
8
8
8
of
of
of
10
10
10
1
D
C
B
A
Rev
Rev
Rev
C
C
C
Publicidad
