Nvidia nForce4 Ultra Manual Del Usuario página 26

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Introduction
21h
22h
23h
24-26h
27h
28h
29h
2A-2Ch
2Dh
2E-32h
33h
34-3Bh
3Ch
3Dh
3Eh
3Fh
40h
41h
42h
43h
44h
45-46h
47h
48h
49h
4A-4Dh
4Eh
4Fh
50h
51h
52h
53-54h
55h
56h
57h
22
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HPM initialization (notebook platform)
Reserved
1. Check validity of RTC value:
e.g. a value of 5Ah is an invalid value for RTC minute.
2. Load CMOS settings into BIOS stack. If CMOS checksum fails, use default value
instead.
3. Prepare BIOS resource map for PCI & PnP use. If ESCD is valid,
take into consideration of the ESCD's legacy information.
4. Onboard clock generator initialization. Disable respective clock
resource to empty PCI & DIMM slots.
5. Early PCI initialization:
-Enumerate PCI bus number
-Assign memory & I/O resource
-Search for a valid VGA device & VGA BIOS, and put it into C000:0.
Reserved
Initialize INT 09 buffer
Reserved
1. Program CPU internal MTRR (P6 & PII) for 0-640K memory address.
2. Initialize the APIC for Pentium class CPU.
3. Program early chipset according to CMOS setup. Example: onboard IDE controller.
4. Measure CPU speed.
5. Invoke video BIOS.
Reserved
1. Initialize multi-language
2. Put information on screen display, including Award title, CPU type, CPU speed ....
Reserved
Reset keyboard except Winbond 977 series Super I/O chips.
Reserved
Test 8254
Reserved
Test 8259 interrupt mask bits for channel 1.
Reserved
Test 8259 interrupt mask bits for channel 2.
Reserved
Reserved
Test 8259 functionality.
Reserved
Reserved
Initialize EISA slot
Reserved
1. Calculate total memory by testing the last double word of each 64K page.
2. Program writes allocation for AMD K5 CPU.
Reserved
1. Program MTRR of M1 CPU
2. Initialize L2 cache for P6 class CPU & program CPU with proper cacheable range.
3. Initialize the APIC for P6 class CPU.
4. On MP platform, adjust the cacheable range to smaller one in case the cacheable
ranges between each CPU are not identical.
Reserved
Initialize USB
Reserved
Test all memory (clear all extended memory to 0)
Reserved
Display number of processors (multi-processor platform)
Reserved
1. Display PnP logo
2. Early ISA PnP initialization

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Nforce4 4x

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