FIC K8M-800T/M Manual página 37

LDT & PCI Bus Control
Upstream LDT Bus Width
This feature allows you to select the range of upstreaming LDT (Lightning
Data Transport) bus width. The options are: 8 bit, 16 bit.
Downstream LDT Bus Width
Th is feature allo ws yo u to select t he rang e of do wn st reaming LDT
(Lightning Data Transport) bus width. The options are: 8 bit, 16 bit.
LDT Bus Frequency
This feature allows you to set the LDT bus frequency.
The options are: Auto, 800 MHz, 600 MHz, 400 MHz, 200 MHz.
PCI1/2 Master WS Write
When Enabled, Writes to the PCI bus are commanded with wait states.
The options are: Enabled, Disabled.
PCI1/2 Post Write
Enables CPU to PCI bus POST write. The options are: Enabled, Disabled.
PCI Delay Transaction
The chipset has an embedded 32-bit p osted write buffer to support delay
transactions cycles. The options are: Enabled, Disabled.
Memory Hole
When you install a Legacy ISA card, this feature allows you to select the
memory hole address range of the ISA cycle when the processor accesses
the selected address area. Please read your card manual for detail informa-
tion . When disabled, the memory hole at the (15-16MB) address will be
treated as a DRAM cy cle when the processor accesses the15~16MB ad-
dress area. The options are: Disabled, 15M - 16M.
VLink Data Rate
This item allows users to select the supported VLink data rate.
The options are: 8X, 4X.
BIOS Setup
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