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IC 401 LC 7860 KA (Digital Signal Processor)
wo| Pinname [vo Functions |
| 1 | TESTI
| § | — | Test pin. Normally not connected.
VCO is generated by connecting
resonance circuit between Al and AO.
(8.6436MHz) is phase output with EFM
signal, and is set to increase frequency
when +",
1 to 2Vpp HF signal is input to EFMIN.
Output from EFMO and BFMO passes
through amplitude limiter and reverse
phase EFM signal is obtained from
both. This performs slice level control.
TEST2
RON SS ee SE
Disk motor contro! output
Focus servo is off when FOCS is HIGH.
ea
The lens is towered by FST and then
FST is HIGH, the lens is gradually
pulled up. FOCS is reset when FZD is
generated.
For focus-in.
*1
Kick pulses, JP+ and JP—, are
generated according to track jump
command.
A jump of the pre-
scribed number of tracks is (1, 4,
16 64).
*2 When 4.3218MHz PCK monitor
terminal/DEMO is HIGH both
SYNC detected from EFM signal
and SYNC of counter are the same
at HIGH.
Set and sount output adjustment pin
function.
Test pin. Normalty
not connected.
De-emphasis is necessary when HIGH.
ON/OFF switch for digital fitter. No
filtering when HIGH.
Test pin
Normally not connected.
*3 Signal output to DAC and signal for
L/R switching and sample hold.
"4 +5V
*5 Signal output for COROM
*6 COROM sync signal
CLV+
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*7 RAM address output
*8 Output state when WE = L and
input state when WE =H. OE is for
input/outptu control.
*7 RAM address output
*8 Output state when WE = L. and
input state when WE = H. OE is for
input/output control.
41
17
Test pin. Normally
not connected.
FSEQ/PCK
CLV+
CLV-
*9 DB7 to DBO:
connected to RAM
data pins.
*10 GND
62 | TEST4
Test pin. Normally not connected.
For CD ROM.
HIGH time interpola-
tion and holding of previous value not
performed.
C1/C2 1-level and 2-level error correc-
tion
PWSY is SYNC combining main and
sub and change from HIGH to LOW is
taken externally. The P,Q, R, S, T, U,
V, and W subcodes are read by sending
8 clock pulses to SBCK.
7.35kHz sync signal output
*11 WRO goes HIGH when data of
subcode QO passes CRC check.
This is taken externally and the
data from SQOUT is read by
sending CQCK.
When data is
required with LSB first, M/L
is
driven LOW. After the micro-
Processor sets RWC to HIGH, the
command is given by output
synchronized with the COCK
command data.
*12 Goes LOW once when power is
mi +
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Tel Phy
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turned on.
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| Xin
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Pin for connection to 8.6436MHz
| 80 | XOuT
l
|
crystal oscillator
IC 101 LA 9200 NM (RF-Amp.+Servo)
IC 402 LC 3517 BS-15 (Static Ram)
IC 601 M 5278D05 (5V Regulator)
FEA+
18
FEAO
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