®
R&S
TS-PMB
9.2 Connector X20
F E D C B A Z
Figure 9-2: Connector X20 (mating side)
Pin
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Pin
Figure 9-3: X20 Pinning Schedule (Version 2.X)
User Manual 1153.5233.12 ─ 05
22
F
E
GA0
PXI_LBR3
PXI_LBR2
PXI_LBL1
AUX1
PXI_TRIG6
GND/NC *1)
PXI_CLK10
PXI_TRIG7
+5V
NC
NC
NP
LABA1
NP
NC
LABB1
NC
NC
LABA2
NC
NC
LABB2
NC
NC
RSA0
RRST#
+12V
+5V
CAN_L
F
E
Rear IO
GA3..0 at GND or N.C.
High Voltage, incompatible PXI
*1) N.C. only in V2.14 (special requirement for use in TS-PCA3 backplane V4.x,
additionally rear-IO-module TS-PRIO required)
D
C
GA1
GA2
PXI_LBR1
GND
PXI_LBL0
AUX2
PXI_LBL3
PXI_TRIG5
AUX4
AUX3
GND
AUX5
+5V
AUX6
IL1
IL3
IL2
+12V
RSDI
RSA1
CAN_H
D
C
Rear IO incompatible PXI
R&S Rear IO control (SPI)
GA5..4 at jumper field, GA5 only TS-PWA3
Interface description
Connector X20
B
A
GA3
GA4
GA5
PXI_LBR0
AUX1
AUX2
GND
PXI_LBL2
PXI_TRIG4
PXI_TRIG3
GND
PXI_TRIG2
PXI_TRIG0
PXI_TRIG1
GND
LABC1
LABD1
LABC2
LABD2
GND
RSDO
+5V
RSCLK
GND
RCS#
B
A
PXI signals
Z
X20
C
NC
O
NC
N
NP
N
NP
E
NC
C
NC
T
NC
O
NC
R
NC
NC
NC
Z
18