Advanced Chipset Features - Abit IN9 32X Manual De Usuario

2.4 Advanced Chipset Features

► Memory Timing Setting
SLI Broadcast Aperture
LDT Frequency
System BIOS Cacheable
NVIDIA CPU Ex
LinkBoost
ECC Control
ECC Uncorrectable
ECC Correctable
:Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5: Previous Values
Memory Timing Setting
Click <Enter> key to enter its submenu:
Parameters
Memory Timing Setting
x tCL (CAS Latency)
x tRCD
x tRP
x tRAS
x Command Per Clock (CMD)
** Advance Memory Settings **
x tRRD
x tRC
x tWR
x tWTR
x tREF
x tREC
:Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5: Previous Values
Memory Timing Setting
You may manually set the DRAM timing parameters through the following sub-items, or leave
them at their default settings according to the SPD (Serial Presence Detect) data stored in the
DRAM.
- tCL (CAS Latency)
- tRCD
- tRP
- tRAS
- Command Per Clock (CMD)
2-16
Phoenix – AwardBIOS CMOS Setup Utility
Advanced Chipset Features
Press Enter
Disabled
5x
Enabled
Disable
Enable
Disabled
Disabled
Disabled
F6: Fail-Safe Defaults
Phoenix – AwardBIOS CMOS Setup Utility
Memory Timing Setting
Setting
Auto
Auto
Auto
Auto
Auto
Auto
Auto(2)
Auto(15)
Auto(3)
Auto(7)
Auto
Auto
F6: Fail-Safe Defaults
F7: Optimized Defaults
Current Value
5
5
5
13
2T
3
18
4
9
7.8uS
35
F7: Optimized Defaults
IN9 32X/IN9 32X -MAX
Item Help
Item Help