Sección 12
Control
12.4.11.3
638
Diagrama de lógica
QA1_OP
QA1_CL
=1
QB1_OP
QB1_CL
=1
QB2_OP
QB2_CL
=1
QC1_OP
QC1_CL
=1
QC2_OP
QC2_CL
=1
QB3_OP
QB3_CL
=1
QB4_OP
QB4_CL
=1
QC3_OP
QC3_CL
=1
QC11_OP
QC11_CL
=1
QC21_OP
QC21_CL
=1
VPQB1
VPQB2
&
VPQC1
VPQC2
VPQB3
VPQB4
VPQC3
QA1_EX2
QC3_OP
QA1_EX3
>1
QC1_CL
QC2_CL
&
QC3_CL
QA1_EX1
IEC04000538 V1 ES
VPQA1
VPQB2
&
>1
VPQC1
1
VPQC2
VPQC3
VPQC11
QA1_OP
QB2_OP
QC1_OP
QC2_OP
QC3_OP
QC11_OP
EXDU_ES
QB1_EX1
VPQB2
VPQC3
&
VP_BC_12
QB2_CL
QC3_OP
BC_12_CL
EXDU_BC
QB1_EX2
VPQC1
VPQC2
&
VPQC3
VPQC11
QC1_CL
QC2_CL
QC3_CL
QC11_CL
EXDU_ES
QB1_EX3
IEC04000539 V1 ES
AB_TRAFO
VPQA1
VPQB1
VPQB2
VPQC1
VPQC2
VPQB3
VPQB4
VPQC3
VPQC11
VPQC21
QA1CLREL
QA1CLITL
1
en04000538.vsd
QB1REL
QB1ITL
en04000539.vsd
1MRK 505 183-UES C
Manual de referencia técnica