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8 CONTROL BOARD
8.1 Technical specifications
Supply voltage (V ~ � Hz.)
Power supply to accessories (Vdc)
Accessories max. load (mA.)
Operating ambient temperature (°C)
Quick-fit connector
Operating logics
Terminal-board connections
Courtesy light timer (min.)
8.2 board components
J1
Low �olta�e inputs/a��essories ter�inal �oar�
J2
Qui�k��it �onne�tor �or re�ei�er r�o�ule at �����/868 MHz
J3
���0V power supply input ter�inal �oar�
Conne�tor �or trans�or�er pri�ary win�in�
J4
J5
Courtesy li�ht ter�inal��oar�
J7
Conne�tor �or trans�or�er se�on�ary win�in�
J�
Motor output �onne�tor
Battery �o�ule �onne�tor
J12
OPEN A
Ra�io si�nal pro�ra��in� push��utton
OPEN B
Ra�io si�nal pro�ra��in� push��utton
OPEN
OPEN push��utton
SET�UP push��utton
SETUP
DS1
Pro�ra��in� �ip�swit�h
LD1
Si�nallin� LED: OPEN input
LD2
Si�nallin� LED: STOP input
Si�nallin� LED: FSW input
LD3
LD4
Si�nallin� LED: SET UP �y�le
LD5
LED si�nallin� �e�ory�stora�e: ra�io �hannel OPEN A
LD6
LED si�nallin� �e�ory�stora�e: ra�io �hannel OPEN B
8.3 Terminal-boards and connectors
Description
Co��an� �e�i�e with N�O� �onta�t
OPEN A
(see �hap� OPERATING LOGICS)
De�i�e with N�C� �onta�t whi�h stops the
STOP
auto�ate� syste�
Ne�ati�e �or OPEN A an� STOP �e�i�es
Closin� sa�ety �e�i�e with N�C� �onta�t (see
FSW
�hap� OPERATING LOGICS)
OPEN COLLECTOR �� V�� �00 �A� output �or
LAMP
�lashin� la�p
Ne�ati�e �or powerin� sa�ety a��essories (FAIL
-TX FSW
SAFE �un�tion)
Ne�ati�e �or powerin� a��essories
+�� V�� �or powerin� a��essories
8.4 DS1 Programming dip-switches
No. Function
� Fail Sa�e
� Anti��rushin� sensiti�ity
�� Not use�
� Carria�e spee�
���0 / ��0
��
�00
��0 / +����
Re�ei�er �o�ule at �����/868
MHz an� �attery �o�ule
Auto�ati� / Se�iauto�ati�
Open/Stop/Sa�ety �e�i�es/Fail�
sa�e/Flashin� la�p �� V��
�
Connected device
OFF
ON
Ena�le�
Not ena�le�
Low
Hi�h
/
/
Hi�h
Low
LD1
LD2
LD3
J1
DS1
LD5
LD6
Fail Safe
I� a�ti�ate�� it ena�les the photo�ell operatin� test �e�ore e�ery
�o�e�ent�
Operating logics
For �oors with an irre�ular �o�e�ent� it re�u�es the sensiti�ity o�
the anti��rushin� �e�i�e to pre�ent unwante� a�tion �y it�
8.5 Operating logics
Logic A (automatic)
Status
Open (pulse)
Opens an� �loses
CLOSED
a�ter pause ti�e
OPENING
No e��e�t
OPEN IN
Resu�es �ountin� o�
PAUSE
pause ti�e (�)
CLOSING
Re�erses �otion
LOCKED
Closes
Logic E (semi-automatic)
Status
Open (pulse)
CLOSED
Opens
OPENING
Lo�ks
OPEN
Closes
CLOSING
Re�erses �otion
LOCKED
Closes
(1) Prevents closing if pulse is maintained.
(2) Prevents closing and�or opening if pulse is
maintained.
0
J8
LD4
J7
J2
J12
J5
J4
J3
Fig. 25
Stop
Fsw
No e��e�t (�)
No e��e�t
Lo�ks (�)
No e��e�t (�)
Resu�es �ountin� o�
Lo�ks (�)
pause ti�e (�)
Lo�ks (�)
Re�erses �otion
No e��e�t (�)
No e��e�t (�)
Stop
Fsw
No e��e�t (�)
No e��e�t
Lo�ks (�)
No e��e�t (�)
No e��e�t (�)
No e��e�t (�)
Lo�ks (�)
Re�erses �otion
No e��e�t (�)
No e��e�t (�)
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