Address Controller; Dram (Dynamic Wndom Access Memory); Bit Shifier; Timing Controller - HP LaserJet II Serie Manual De Instrucciones

HP 33440/HP 33449 COMBINED SERVICE MANUAL
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Figure 5-17. HP 33440 interface PCA Block Diagram
~ddress Controller
The address contro~er is implemented as a single gate array circuit (GA1). Jumpers attached to
the gate array enable the ROM address region to be changed. The ROM has a mtimum mpaci~
of 1 Mbyte and is used in four separate sedions. The address controller dso outputs address
information enabfing amess h data in the Interface PCA'S DRAM (bmum mpaci@ of 512
~ytes) and e~ansion DW (mAmum mpacity of 4 Mbytes).
DRAM (Dynamic Random Access Memory)
The DRAM is a dynamic random access memory with a @mum mpaci@ of 512 ~@s. It
stores printing and font information input from the efiernd device. It dso stores page formatting
information and other parameters required by the internal microprocessor. The microprocessor
subdivides the DRAM memory space as required. An e~ansion memory board a be added to
increase the DRAM by 1, 2, or 4 Mb~es, depending upon the board purchased.
Bit
Shifter
The bit shifter is used to offset or overlay printed characters, and to shifi data by 1 to 15 bits.
fiming Controller
The timing controller generates' timing signals needed when data is written to or read from
DW. It dso generates DRAM refresh signals.
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